1. Field of the Invention
This invention relates to a multilevel semiconductor integrated circuit device in which semiconductor IC chips and electronic components are integrated with high integration and compact installation,
2. Description of the Related Art
Semiconductor integrated circuit devices having semiconductor IC chips and electronic components integrated therein are used in various electronic circuit devices. Conventional semiconductor integrated circuit devices have two-dimensionally installed ICs on printed circuit boards (referred to as circuit boards hereafter). Those ICs are packaged in molded plastic cases and usually soldered onto the circuit boards.
The conventional semiconductor integrated circuit devices will be explained by way of integrated memory circuits in which monolithic memory IC chips are installed.
Recent miniaturization of electronic apparatus increasingly requires integrated memory circuits with higher integration and more compact memory IC installation. However, the conventional integrated memory circuits having two-dimensionally installed memory ICs have the following problems.
(1) Recent high performance CPUs demand a larger memory capacity in the main memory circuit, The memory capacity can be doubled by using memory ICs at the same capacity, not only twice the number of memory ICs are required, but the circuit board areas for the memory ICs also increase twice or more. Consequently, the miniaturization of the electronic circuit devices having integrated memory circuits can not be attained.
(2) Increasing the circuit board areas for the reason described in (1) raises the production cost of the integrated memory devices because the circuit board is expensive. Moreover, it results in longer wirings on the circuit boards, increasing wiring impedance. Consequently, the devices suffer from the deterioration of transmission characteristic such as signal waveform change, and deterioration of response characteristic for high frequency signals.
(3) The circuit board areas for memory ICs are slightly reducible using memory ICs whose package sizes are made smaller by narrowing the pitches between their terminals. However, since conventional chip mounting techniques can not be applied to the memory ICs having narrow pitched terminals, sophisticated mounting techniques are required.
In order to overcome the problems of the conventional integrated memory circuits of the two-dimensional installation type, for example, Japanese Patent Publication No. 5-14427 and U.S. Pat. No. 4,982,265 disclose multilevel integrated memory circuits on which a plurality of memory IC chips are installed in multiple levels. On these multilevel integrated memory circuits, lead terminals for selectively accessing any desired one of the IC chips in respective levels (referred to as selection terminals hereafter) that are formed in different shapes and provided at different positions. These terminals are individually and independently connected to the circuit board, while the terminals having the common functions for the memory IC chips in respective levels, such as power supply terminals or ground terminals (referred to as common terminals hereafter) are interconnected to each other and coupled with one and the same pad on the circuit board by soldering or other techniques.
However, such conventional multilevel integrated memory circuits with lead terminals connected in the above-described manner have the following problems.
(1) For common terminals, because the lead terminals of the memory IC chips in respective levels are typically soldered so as to be connected to each other without any modification, the physical strength in the connection portions is insufficient. Furthermore, their smaller connection areas cause electrical instability due to contact resistance variation. The electrical connections are especially instable when the lead terminal shapes change, and so the connections sometimes fail.
(2) Because all the common terminals of the memory IC chips at the respective levels are soldered together, when there is a defect in a memory IC chip in any of the levels and a repair is required, all the levels need to be removed even for repairing only one level.
Japanese Laid-Open Patent Publication No. 4-26152 discloses a multilevel integrated memory circuit designed to solve these problems. In the multilevel integrated memory circuit, each memory IC chip for multilevel installation has its terminals at different positions so as to prevent the terminals from overlapping the terminals of the other memory IC chips. More specifically, the lead terminals of one memory IC chip are provided only in one assigned portion of the sides of the memory IC chip. The assigned portion is different from those of the other IC chips. Accordingly, after the multilevel installation, the terminals of the respective memory IC chips are separately and independently connected to the circuit board without overlapping each other. This terminal arrangement in the multilevel integrated memory circuit disclosed in this publication allows only a memory IC chip in a specific level to be removed, whereby the repair efficiency is improved.
However, due to this terminal arrangement, each IC chip has a smaller number of terminals than that of conventional IC chips unless the pitches between the terminals are narrowed. This sometimes causes the IC functions to be limited.